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Processing Instruction
Results: 1077

#	Item
801	AN ALTERNATIVE TO BRANCH PREDICTION: P R E - C O M P U T E D BRANCHES Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2008-11-17 09:44:18 Central processing unit Branch predictor Assembly languages Hazard Branch misprediction Instruction set CPU cache Addressing mode Delay slot Computer architecture Computer hardware Computer engineering
802	SIMULATING SOME ADVANCED PROCESSING TECHNIQUES INTO A SUPERSCALAR ARCHITECTURE Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-05-17 01:41:51 Central processing unit Classes of computers Computer memory Parallel computing CPU cache Superscalar Cache Reduced instruction set computing Instruction-level parallelism Computer hardware Computer architecture Computing
803	Buletinul Stiintific al Universitatii “Politehnica” din Timisoara, ROMANIA Seria AUTOMATICA si CALCULATOARE PERIODICA POLITECHNICA, Transactions on AUTOMATIC CONTROL and COMPUTER SCIENCE Vol[removed]), 2002, ISSN 1224- Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2005-12-13 09:40:43 Central processing unit Instruction set architectures Assembly languages MIPS architecture Processor register Addressing mode Microarchitecture Instruction set Branch predictor Computer architecture Computer hardware Computer engineering
804	Microsoft Word - Final_versionEuroSim2007 _2_.doc Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2007-09-24 05:11:16 Branch predictor Central processing unit Software optimization Microarchitecture Alpha 21264 Instruction-level parallelism Benchmark Computer performance Simulation Computer architecture Computing Computer engineering
805	ADVANCED TECHNIQUES FOR IMPROVING PROCESSOR PERFORMANCE IN A SUPERSCALAR ARCHITECTURE Gordon B. STEVEN, University of Hertfordshire, Department of Computer Science, UK, E-mail: [removed] Lucian VINTAN, Adrian F Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-05-17 01:41:23 Computing Classes of computers Parallel computing CPU cache Cache Superscalar Microarchitecture Reduced instruction set computing Instruction-level parallelism Computer architecture Computer hardware Central processing unit
806	Procedure Work Instruction Control P4[removed]Rev. E Add to Reading List Source URL: www.qualitycoils.com Language: English - Date: 2012-03-18 17:26:19 Computing Central processing unit Instruction set Document management system
807	GPU computing CUDA Rossen Radev Add to Reading List Source URL: cluster.phys.uni-sofia.bg Language: English - Date: 2008-01-29 12:03:20 GPGPU Graphics hardware Computing CUDA Nvidia Tesla Graphics processing unit Nvidia Quadro Nvidia Ion Instruction set Nvidia Computer hardware Video cards
808	060-computer-Geller[removed] Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2007-12-05 00:43:29 Central processing unit CPU cache Cache Computer memory Branch predictor Microarchitecture Parallel computing Superscalar Instruction-level parallelism Computer architecture Computer hardware Computer engineering
809	059-computer-Florea[removed] Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2007-12-05 00:43:29 Central processing unit Computer memory Runahead CPU cache Microarchitecture Memory-level parallelism Parallel computing Branch predictor Instruction set Computer architecture Computer hardware Computer engineering
810	PRE-COMPUTED BRANCH “PREDICTION” Lucian N. VINTAN, Marius SBERA, Adrian FLOREA * “Lucian Blaga” University of Sibiu, Computer Science Department, Sibiu, ROMANIA E-mail: [removed], aflorea@vectr Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-05-17 01:48:51 Central processing unit Branch predictor Assembly languages Hazard Branch misprediction CPU cache Instruction set Delay slot Addressing mode Computer architecture Computer hardware Computer engineering

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